BITS Pilani

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Microelectronics and VLSI Design

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Microelectronics and VLSI Design

Microelectronics and VLSI Design

Microelectronics education is a collaborative, multidisciplinary activity, involving the combined efforts of system architects, circuit designers, device engineers, software developers, and process engineers. India, with capabilities in VLSI (Very Large Scale Integration) design and software development, has potentially captured a larger share of the market by focussing on these segments.
 
Research in VLSI / CAD (Computer Aided Design) works toward developing new algorithms and design methodologies that allow the VLSI designers to design correct, faster, smaller and more power-efficient integrated circuits. Research in VLSI/CAD has proved to be one of the important reasons for the VLSI boom in recent years. Applications of such research abound in current industrial practice.
 
Oyster Laboratory (Microelectronics and VLSI Lab at BITS Pilani) is involved in the design and implementation of Analogue, Digital, RF and Mixed-signal VLSI circuits and systems. Applications in Signal Processing are also being developed. Micro and nano-scale semiconductor process technologies ranging from 0.35μm to 65nm CMOS process technologies are being investigated for various VLSI System-On-Chip implementations.
 
 

Subareas

  • Digital VLSI Design
  • Analog and Mixed Signal Design
  • FPGA Design
  • Asynchronous System Design
  • Device Modelling
  • Micro-Electro Mechanical Systems (MEMS)

Projects

On-going Projects
 
  • Designed 8-bit Asynchronous pipelined ADC in UMC 180nm Technology.
    Funding Agency: BITS SEED GRANT
 
Completed Projects
  • Study of Electrical Behaviour of Nanocrystalline Silicon Thin-Film Transistor (nc-TFT) (2011-2013)
         Funding Agency:UGC
         PI: Dr. Navneet Gupta
  • Modeling and study of polycrystalline silicon for solar cells and thin-film transistors (2007-2010)
    Funding Agency: DST under FAST TRACK PROPOSALS FOR YOUNG SCIENTISTS.
    PI: Dr. Navneet Gupta

Publications

2014:
  1. Prachi Sharma and Navneet Gupta, “Threshold Voltage Modeling on Nanocrystalline Silicon Thin-Film Transistors”, J.Electron Dev., 1608-1612, vol. 19, (2014).
  2. Priya Gupta, Ishan Munje, Nikhil Kaswan , Anu Gupta , Abhijit Asati  “Analysis & Implementation of Ultra Low-Power 4-bit CLA in subthreshold regime”  Selected to be published on IEEE International Conference on Circuit, Power and Computing Technologies” (ICCPCT), March 20th-21st 2014, Tamilnadu .
     
2013:
  1. A.K.Sharma and Navneet Gupta, "Microelectromechanical System (MEMS) Switches for Radio Frequency Applications-A Review", Sensors and Transducers, vol.148, pp.11-21, 2013. 
  2. Ashish K. Sharma and Navneet Gupta, “Electromagnetic Modeling and Parameter Extraction of RF-MEMS Switch” Microsystem Technologies: Springer-Verlag Berlin. (Nov-2013). DOI:10.1007/s00542-013-1952-3 (SCI indexed).
  3. Ashish K. Sharma and Navneet Gupta, “Investigation of Actuation Voltage for Non-Uniform Serpentine Flexure Design of RF-MEMS Switch”, Microsystem Technologies: Springer-Verlag Berlin, (Oct-2013). DOI: 10.1007/s00542-013-1930-9. (SCI indexed).
  4. Ashish K. Sharma and Navneet Gupta, “Analytical Modeling for Spring Constant of Non-Uniform Serpentine Radio Frequency-Micro Electro Mechanical System Switch” Advanced Science, Engineering and Medicine, American Scientific Publishers, 5 (12), 1322-1325, (2013).
  5. Bharat Kumar Potipireddi and Dr. Abhijit Asati, "Automated HDL Generation of Two’s Complement Wallace Multiplier with Parallel Prefix Adders," International Journal of Electronics and Communication Engineering & Technology (IJECET),  Volume 4, Issue 3, May – June (2013). ISSN 0976 – 6464(Print), ISSN 0976 – 6472(Online).
  6. Bharat Kumar Potipireddi and  Abhijit Asati, "Automated HDL Generation of Two’s Complement Dadda Multiplier with Parallel Prefix Adders," International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering (IJAREEIE), Vol. 2, Issue 6, June  2013. ISSN 2320 - 3765 (Print), ISSN  2278 – 8875 (Online).
  7. Rikmantra Basu, B. Mukhopadhyay and P. K. Basu, “Analytical Model for    Threshold Base Current of a Transistor Laser with Multiple Quantum Wells in the Base”, IET – Optoelectronics Journal, vol. 7, no. 3, pp. 71-76, 2013
  8. Rikmantra Basu, Vedatrayee Chakraborty, B. Mukhopadhyay and P. K. Basu, “Predicted Performance of Ge/GeSn Hetero- Phototransistors on Si Substrate at 1.55 μm”, Optical and Quantum Electronics Journal, 2013 (Provisionally Accepted).
  9. Priya Gupta, Anu Gupta and Abhijit Asati “A Review on Ultra Low Power Design Technique: Subthreshold Logic ” International Journal of Computer Science and Technology-IJCST,Vol.4, Issue Spl-2, April-June 2013, ISSN: 0976-8491 (Online)  ISSN : 2229-4333 (Print). 
  10. Nitin Chaturvedi, S Gururnarayanan “Study of Various Factors Affecting performance of Multi-core architectures” in International Journal of Distributed and Paraellel Systems (IJCSI), Volume 1, No 2, September 2013. 
  11. Sneh lata Murotiya and Anu gupta (2013), " Design of CNTFET based 2-bit ternary ALU for nano-electronics, International Journal of Electronics, Taylor & Francis, DOI: 10.1080/00207217.2013.828.
  12. Sneh Lata Murotiya and anu gupta (2013), “Design of CNTFET-based Radiation hardened Latches” will be published in European Journal of Scientific Research, Volume 117 Issue 1.
  13. Bhawani Shankar, Sanjeev K. Gupta, William R. Taube, Jitendra Singh, Abhijit Asati and J. Akhtar "Breakdown Voltage Enhancement in 4H-SiC Schottky Diode Employing Field Plate Edge Termination using High-k Dielectrics," International Conference on Silicon Carbide and Related Materials 2013 (ICSCRM 2013), Miyazaki, Japan, 2nd October 2013. 
  14. Ishit Makwana, Shruti Mittal, Nitin Chaturvedi and Nidhi Chaturvedi “Optimization of AlGaN/GaN HEMT based PH sensor for breast cancer detection”,  in “ 37th workshop on compound semiconductor devices and Integrated circuits, 26-29th May. 2013, pp 85-86 Warnemuende, Germany.
  15. Sachin Maheshwari, Himadri Singh Raghav and Dr. Anu Gupta, " Characterization of Logical Effort for Improved Delay" VLSI Design and Test, Communications in Computer and Information Science, Vol. 382, pp. 108–117, 2013. (© Springer-Verlag Berlin Heidelberg 2013)
  16. Sachin Maheshwari, Rameez Raza, Pramod Kumar and Dr. Anu Gupta, " Convex Optimization of Energy and Delay using Logical Effort Method in Deep Sub-Micron Technology" VLSI Design and Test), Communications in Computer and Information Science, Vol. 382, pp. 185–193, 2013. (© Springer-Verlag Berlin Heidelberg 2013).
  17. Sivam Prasad Kopparthy, Ishit Makwana and Dr. Anu Gupta, "An Asynchronous 8 bit 5MS/s Pipelined ADC for Biomedical Sensor Based Applications",IEEE International Conference on Electronics, Computing and Communication Technologies, (IEEE CONNECT), pp.1-6, Jan. 17-18, Bangalore, 2013. 
  18. Sneh Lata Murotiya, Anu Gupta, "CNTFET Based Design of Content Addressable Memory Cells", 4th IEEE ICCCT – 2013, MNNIT Allahabad, pp.1-4, Sep.20-22, 2013.
  19. Sneh Lata Murotiya, Anu Gupta, “Performance Evaluation of CNTFET based Dynamic Dual Edge Triggered Register”, 1st IEEE ICAES – 2013, CEERI Pilani, pp. 180-183, Sep. 21-23, 2013.
  20. Sneh Lata Murotiya, Anu Gupta, “DESIGN AND ANALYSIS OF CNTFET BASED D FLIP-FLOP”, presented in ICCS – 2013, BKBIET Pilani and published in IJECET, vol.4, issue 7 pp. 144-149, 2013.
  21. Sneh Lata Murotiya, Anu Gupta, “Performance Evaluation of CNTFET based DTCAM cell”, IEEE Conference INDICON – 2013, IIT Mumbai. 
  22. Rikmantra Basu, Vedatrayee Chakraborty, B. Mukhopadhyay and P. K. Basu, “Performance Analysis of Ge/GeSn Hetero- Phototransistors”, International Conference on Microwave and Photonics (ICMAP), ISM  Dhanbad, December 15 -17, 2013. 
  23. Priya Gupta, Akshay Kumar Sharma, Pratishtha Dehadray, Anu Gupta “Design and Implementation of low power TG Full Adder design in subthreshold regime” IEEE International Conference on Intelligent Interactive Systems and Assistive Technologies, August 2-3, 2013, Coimbatore, INDIA 
  24. Nikhil Kaswan , Ishan Munje, Yash Kothari , Priya Gupta, Anu Gupta “Implementation of high speed energy efficient 4-bit binary CLA based incrementer /decrementer”  in 2013 International Conference on Advanced Electronic Systems (ICAES),  Sept. 21-23 2013, CEERI Pilani. 
  25. Priya Gupta, Ishan Munje, Nikhil Kaswan , Anu Gupta , Abhijit Asati  “Analysis & Implementation of Ultra Low-Power 4-bit CLA in subthreshold regime”  Selected to be published on IEEE International Conference on Circuit, Power and Computing Technologies” (ICCPCT), March 20th-21st 2014, Tamilnadu .  
  26. Prachi Sharma and Navneet Gupta, "Nanocrystalline Silicon Thin Film Transistor (nc-Si:H TFTs)-A Device for Display Panels",  Int. Conf. on Comm. Sys.(ICCS-2013), B K Birla Institute of Engineering & Technology (BKBIET), Pilani,18-20 October, 2013. 
  27. Prachi Sharma and Navneet Gupta, “Model for Drain Current based on the Exponential Distribution of Tail States for Nanocrystalline Silicon Thin Film Transistor” 3rd IEEE International Advance Computing Conference (IACC-2013), Ghaziabad (UP), India, Feb. 22-23, 2013. 
  28. Rashi Khatri, S Sheth, Navneet Gupta, “Modeling of Zinc Oxide (ZnO) based Thin-Film Transistors (TFTs)”, 2nd Int. Symp. on Semiconductor Materials and Devices (ISSMD-2), Univ. of Jammu, January 31 to February 2, 2013.
  29. Ashish K. Sharma and Navneet Gupta, " Material Selection Approach for Dielectric Layer in RF-MEMS Switch", International Conference on Emerging Technologies - Micro to Nano (ETMN-2013), BITS, Pilani - KK Birla Goa Campus, India, Feb. 23-24,  2013. 
  30. Abhishek Mukherjee, Prachi Sharma and Navneet Gupta, “Modeling of Field Effect Mobility using Grain Boundaries on Nanocrystalline Silicon Thin-Film Transistor (nc-Si TFT)” Second International Symposium on Semiconductor Materials and Devices (ISSMD-2), Jan. 31 - Feb. 2, 2013. 
  31. Nitin Chaturvedi, S Gurunarayanan “An Adaptive Block Pinning Cache for Reducing Network Traffic in Multi-Core Architectures” 2013 IEEE International Conference on Computational Intelligence and Communication Network, ICCN-2013, Sept 27-29 ,2013.
  32. Nitin Chaturvedi, Pawan Sharma, S Gurunarayanan “An Adaptive Coherence Protocol with Adaptive Cache for Multi-core Architectures” International Conference on Advanced Electronic Systems, ICAES-2013, 21-23, September 2013.
  33. Siddharth Malhotra , Abhinav Mishra, Rakesh B R , Anu Gupta, "Frequency Compensation in Two-Stage Operational Amplifiers for Achieving High 3-dB Bandwidth”  IEEE PrimeAsia 2013 Conference held at GITAM University, Visakhapatnam Campus, 19th -21st December 2013.
  34. Abhilash K N, Shakthi Bose, Anu Gupta, " A High Gain, High CMRR Two-Stage Fully Differential Amplifier Using gm/Id technique for Bio-medical Applications", IEEE PrimeAsia 2013 Conference held at GITAM University, Visakhapatnam Campus, 19th -21st December 2013
  35. Ganesh Raj,  Ankur Gupta , Dr. Anu Gupta, " Self timed High speed 8-bit SAR ADC in 0.35um", IEEE Conference INDICON – 2013, IIT Mumbai
  36. Abhishek Mukherjee and Abhijit Asati, "Generic Modified Baugh Wooley Multiplier," International Conference on Circuits, Power and Computing Technologies (ICCPCT- 2013), Kumaracoil (Tamilnadu), INDIA, 21-22 March 2013.
  37. Ashish K. Sharma and Navneet Gupta, “Electromagnetic Modeling of Non-Uniform serpentine flexure based RF-MEMS switch” IEEE International conference on Advance Electronic Systems (ICAES), CSIR-CEERI Pilani, India, sep 21-23, 2013.
  38. A K. Sharma and Navneet Gupta, "Switching time-analysis for non-uniform serpentine flexure based RF-MEMS switched”, IEEE 2nd Students Conference on Engineering and Systems, Motilal Nehru National Institute of Technology (MNNIT) Allahabad, India, April 12-13,  2013. 
  39. Jaskaran Singh Grover , Anu Gupta ,"Studying Crosstalk Trends for Signal Integrity on Interconnects using Finite Element Modeling", COMSOL Conference 2013 October 17 - 18, 2013, Bangalore.

Research Scholars

Prachi Sharma, Priya Gupta

Layout

Layout of 8-bit Asynchronous ADC with pad frame in UMC180nm Technology.

An institution deemed to be a University estd. vide Sec.3 of the UGC Act,1956 under notification # F.12-23/63.U-2 of Jun 18,1964

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