Journals:

• Kanika Monga, Nitin Chaturvedi, S. Gurunarayanan, " Design of a STT-MTJ Based Random-Access Memory With In-situ Processing for Data-Intensive Applications," in IEEE Transactions on Nanotechnology, vol. 21, pp. 455-465, 2022, doi: 10.1109/TNANO.2022.3199230 (SCI Indexed).
• Kanika Monga, Nitin Chaturvedi, S. Gurunarayanan, "A Dual-Mode In-Memory Computing Unit Using Spin Hall-Assisted MRAM for Data-Intensive Applications," in IEEE Transactions on Magnetics, vol. 57, no. 4, pp. 1-10, April 2021, Art no. 1400210, doi: 10.1109/TMAG.2021.3059268. (SCI Indexed).
• Kanika Monga, Nitin Chaturvedi, S. Gurunarayanan, “Design of a novel CMOS/MTJ-based multibit SRAM cell with low store energy for IoT applications”, in International Journal of Electronics, Taylor & Francis, Vol. 107, Issue: 6, pp no. 899-914, 2020, DOI: 10.1080/00207217.2019.1692245. (SCI Indexed).
• Kanika Monga, Nitin Chaturvedi, S. Gurunarayanan, "Energy-efficient data retention in D flip-flops using STT-MTJ", Circuit World, Emerald Insight Vol. 46 No. 4, pp. 229-241. 2020, https://doi.org/10.1108/CW-09-2018-0073. (SCIE Indexed)
• Kanika Monga, Kunal Harbhajanka, Arush Srivastava, Nitin Chaturvedi, S. Gurunarayanan “Design of an MTJ/CMOS based Asynchronous System for Ultra-Low Power Energy Autonomous Applications” in Journal of Circuits, Systems and Computers. World Scientific, 2020, DOI: 10.1142/S0218126621500584. (SCIE Indexed).
• Kanika Monga, Meetha V Shenoy Nitin Chaturvedi, S. Gurunarayanan, “Design of a tunable delay line with on-chip calibration to generate process invariant PWM signal for in-memory computing”, Analog Integrated Circuits and Signal Processing, Springer, 2023. (SCI Indexed)

Conferences:

• Kanika Monga, Sunit Behera, Nitin Chaturvedi, S. Gurunarayanan, “Design of In-Memory Computing Enabled SRAM Macro” in 2022 IEEE 19th India Council International Conference (INDICON-2022), CUSAT, Kochi, 24-26 Nov, 2022.
• Monga, S. Aggarwal, N. Chaturvedi and S. Gurunarayanan, "A Novel Decoder Design for Logic Computation in SRAM: CiM-SRAM," 2021 IEEE 18th India Council International Conference (INDICON), pp. 1-4, 2021.
• Kanika Monga, Nitin Chaturvedi, S. Gurunarayanan, “Design of a Low Power Approximate Adder based on Magnetic Tunnel Junction for Image Processing Applications” in 2021 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), Hsinchu, Taiwan, April 19-22, 2021.
• Kanika Monga, L. Maheshwari, N. Chaturvedi and S. Gurunarayanan, "Twin-Coupled Sense Amplifier to improve margin in 1T-1MTJ based MRAM array," in 24th International Symposium on VLSI Design and Test (VDAT-2020), Bhubaneswar, India, 2020, pp. 1-4, doi: 10.1109/VDAT50263.2020.9190177.
• Kanika Monga, N. Chaturvedi and S. Gurunarayanan, "Design of a Low Power 11T-1MTJ Non-Volatile SRAM Cell with Half-Select Free Operation," in 2020 IEEE 17th India Council International Conference (INDICON-2020), New Delhi, India, 2020, pp. 1-5.
• Kanika Monga, Saurabh, Nitin Chaturvedi and S. Gurunarayanan, “Logic in Memory Design using Spin Hall Effect Assisted Magnetic Tunnel Junction” presented at 33rd International Conference on VLSI Design & The 19th International Conference on Embedded Design (VLSID 2020), Bangalore, India, Jan 4-8, 2020.