Quantum Convolutional Neural Network for Medical Image Classification: A Hybrid Model
Ria Khatoniar, Vishu Vyas, Videet Acharya, Anshul Saxena, Amit Saxena, Rahul Neiwal Kunal Korgaonkar
International Conference on Trends in Quantum Computing and Emerging Business Technologies 2024
[Conference on Quantum Technologies]
Characteristics of Deep Learning Workloads in Industry, Academic Institutions and National Laboratories.
Natasha Meena Joseph, S. Sai Vineet, Kunal Korgaonkar, Arnab K. Paul;
https://dl.acm.org/doi/abs/10.1145/3571306.3571428
International Conference on Distributed Computing and Networking 2023
[Top Systems & Networking Venue]
A Data-Centric Approach for Analyzing Large-Scale Deep Learning Applications.
S. Sai Vineet, Natasha Meena Joseph, Kunal Korgaonkar, Arnab K. Paul;
https://dl.acm.org/doi/abs/10.1145/3571306.3571414
International Conference on Distributed Computing and Networking 2023
The Bitlet Model: A Parameterized Analytical Model to Compare PIM and CPU Systems;
R. Ronen, A Eliahu, N. Peled, O. Leitersdorf, K. Korgaonkar, A. Chattopadhyay, B. Perach, S. Kvatinsky;
https://dl.acm.org/doi/full/10.1145/3465371
ACM Journal on Emerging Technologies in Computing Systems (JETC) 2021
[Top Journal on Emerging Technologies]
A Deluge of Processing-in-Memory Frameworks and How Analytical Modeling Could Help!;
K. Korgaonkar, R. Ronen, A. Chattopadhyay, S. Kvatinsky;
http://cseweb.ucsd.edu/~kkorgaon/papers/nvmw-2020-deluge-Of-PIM.pdf
Non-Volatile Memories Workshop (NVMW) 2020
The Bitlet Model: Defining a Litmus Test for the Bitwise Processing-in-Memory Paradigm;
K. Korgaonkar, R. Ronen, A. Chattopadhyay, S. Kvatinsky;
https://software.intel.com/sites/default/files/managed/3b/a6/session3-talk3.pdf
Compilers, Architecture and Tools Conference (CATC) 2019
[Industry Event] [On Invitation]
Vorpal: Vector Clock-Inspired Ordering For Large Persistent Memory Systems;
K. Korgaonkar, J. Izraelevitz, J. Zhao, S. Swanson;
https://dl.acm.org/doi/abs/10.1145/3293611.3331598
ACM’s Principles of Distributed Computing Conference (PODC) 2019
[Top Conference] [Acceptance rate: 29%]
To Cache Or To Bypass? A Fine Balance For Emerging Mem. Tech. Era;
K. Korgaonkar, I. Bhati, H. Liu, J. Gaur, S. Manipatruni, S. Subramoney, T. Karnik, S. Swanson, I. A. Young, H. Wang;
http://cseweb.ucsd.edu/~kkorgaon/papers/nvmw-2019-high-density-caches.pdf
Non-Volatile Memories Workshop (NVMW) 2019
Density Tradeoffs of NVM as a Replacement for SRAM LLCs;
K. Korgaonkar, I. Bhati, H. Liu, J. Gaur, S. Manipatruni, S. Subramoney, T. Karnik, S. Swanson, I. A. Young, H. Wang;
https://ieeexplore.ieee.org/document/8416837
ACM/IEEE’s International Symposium on Computer Architecture (ISCA) 2018
[Top Conference] [Top Journal of Computer Architecture - SIGARCH] [Acceptance rate: 17%]
Granular Computing: Blending Terabit Network with Terabyte Main Memories;
K. Korgaonkar, Shelby Thomas;
http://cseweb.ucsd.edu/~kkorgaon/papers/arm-research-2018-granular-computing.pdf
ARM Industry-Academia Research Summit 2018
[Industry Event] [On Invitation]
Characterization of User's Behavior Variations for Design of Replayable Mobile Workloads;
S. Patil, Y. Kim, K. Korgaonkar, I. Awwal, T. Rosing;
https://link.springer.com/chapter/10.1007/978-3-319-29003-4_4
Springer LNICST’s Mobile Computing, Applications, and Services Conference (MobiCase) 2015
[Top Conference] [Acceptance rate: 37%]
CPU or GPU Bound?: In-Depth Case-Studies of Mobile Gaming Workloads;
K. Korgaonkar, K. Sankaranarayanan, S. Srinivas;
Intel Internal Research Report, 2014 (Confidential)
[Industry Impact] [Intel Internal Technical Report]
Implications of Shared-Data Synchronization Techniques on Multi-Core Energy Efficiency;
Gautham, K. Korgaonkar, Patanjali S., S. Balachandran and V. Kamakoti;
https://www.usenix.org/conference/hotpower12/workshop-program/presentation/gautham
Usenix’s Workshop on Power-Aware Computing and Systems (HotPower) 2012
[Top Usenix Event] [Acceptance rate: 25%]
Size-proportional signature sharing for transactional memory systems;
K. Korgaonkar, Kashyap G. and V. Kamakoti;
http://cseweb.ucsd.edu/~kkorgaon/papers/faspp-2012-sizeprop-signature-for-tm.pdf
Workshop on Future Architecture Support for Parallel Programming (FASPP) 2012
Reconstructing hardware transactional memory for workload optimized systems;
K. Korgaonkar, P. Jain, D. Tomar, K. Garimella and V. Kamakoti;
https://link.springer.com/chapter/10.1007/978-3-642-24151-2_1
Springer LNCS’s Advanced Parallel Processing Technologies Symposium (APPT) 2011
Thread synchronization: from mutual exclusion to transactional memory;
K. Korgaonkar and V. Kamakoti;
https://www.tandfonline.com/doi/abs/10.4103/0256-4602.83551
Institution of Electronics and Telecommunications Engineer (IETE) Review 2011
HTM Design Spaces: Complete Decoupling from Caches;
K. Korgaonkar, G. Kurian, M. Gautam and V. Kamakoti;
https://dl.acm.org/doi/10.1145/1531793.1531809
ACM’s Operating Systems Review (Position Paper) 2009
An Institute of Eminence
