Peer Reviewed Journals

1. Ruma S R, Vita Pi-Ho Hu, and M. Gupta, “Insights into Threshold Voltage Variability in Negative Capacitance Junctionless Transistor,” IEEE Journal of the Electron Device Society. (Accepted)
2. Ruma S R and M. Gupta, “Sub-60 mV/Decade Dynamic Subthreshold Swing in Bulk Negative Capacitance Junctionless MOSFET,” IEEE Transactions on Electron Devices, vol. 71, no. 11, pp. 7156-7161, 2024.
3. K. Nirala, S. Semwal, M. Gupta, and A. Kranti, “Energy and Disturbance Analysis of 1T-DRAM With Nanowire Gate-All-Around RFET,” IEEE Transactions on Electron Devices, vol. 71, no. 5, pp. 2950-2956, 2024.
4. M. Gupta and V. P. H. Hu, “Improved Scalability of Negative Capacitance Junctionless Transistors with Underlap Design,” IEEE Transactions on Electron Devices, vol. 70, no. 8, pp. 4043-4048, 2023.
5. M. Gupta and V. P. H. Hu, “Sensitivity Analysis of Negative Capacitance Junctionless Transistor and Design Aspects for High Performance Applications,” IEEE Transactions on Electron Devices, vol. 68, no. 8, pp. 4136-4143, 2021.
6.  M. Gupta and V. P. H. Hu, “Influence of Channel Doping on Junctionless and Negative Capacitance Junctionless Transistors,” Journal of Solid-State Science and Technology, vol. 10, 065009, 2021.
7. Kranti and M. Gupta, “Junctionless Device Cross-section: A key Aspect for Overcoming Boltzmann Tyranny,” ECS Transactions, vol. 97, no. 5, pp. 39-44, 2020. (Invited)
8. M. Gupta and V. P. H. Hu, “Negative Capacitance Junctionless Device with Mid-gap Workfunction for Low Power Applications,” IEEE Electron Device Letters, vol. 41, no. 3, pp. 473-476, 2020.
9. M. Gupta and A. Kranti, “Bi-directional Junctionless Transistor for Logic and Memory Applications,” IEEE Transactions on Electron Devices, vol. 66, no. 10, pp. 4446-4452, 2019.
10. M. Gupta and A. Kranti, “Relevance of Device Cross-Section to Overcome Boltzmann Switching Limit in 3D Junctionless Transistor,” IEEE Transactions on Electron Devices, vol. 66, no. 9, pp. 2704-2709, 2019.
11. Mokkapati, N. Jaiswal, M. Gupta, and A. Kranti, “Gate-All-Around Nanowire Junctionless Transistor based Hydrogen Gas Sensor” IEEE Sensors Journal, vol. 19, no. 13, pp. 4758-4764, 2019.
12. M. Gupta and A. Kranti, “Regaining Switching by Overcoming Single Transistor Latch Effect in Ge Junctionless MOSFETs,” IEEE Transactions on Electron Devices, vol. 65, no. 9, pp. 3600-07, 2018.
13. M. Gupta and A. Kranti, “Raised Source/Drain Germanium Junctionless MOSFET for Subthermal OFF-to-ON Transition,” IEEE Transactions on Electron Devices, vol. 65, no. 6, pp. 2406-12, 2018.
14. M. Gupta and A. Kranti, “Steep-switching Germanium Junctionless MOSFET with Reduced Off-state Tunneling,” IEEE Transactions on Electron Devices, vol. 64, no. 9, pp. 3582-87, 2017.
15. M. Gupta and A. Kranti, “Variation of Threshold Voltage With Temperature in Impact Ionization-Induced Steep Switching Si and Ge Junctionless MOSFETs,” IEEE Transactions on Electron Devices, vol. 64, no. 5, pp. 2061-66, 2017.
16. M. Gupta and A. Kranti, "Hysteresis Free Negative Total Gate Capacitance in Junctionless Transistors," Semiconductor Science and Technology, vol. 32, no. 9, pp. 095014, 2017.
17. Gupta and A. Kranti, “Transforming Gate Misalignment into a Unique Opportunity to Facilitate Steep Switching in Junctionless Nanotransistors,” Nanotechnology, vol. 27, no. 45, pp. 455204, 2016.
18. M. Gupta and A. Kranti, “Sidewall Spacer Optimization for Steep switching Junctionless Transistors,” Semiconductor Science and Technology, vol. 31 no. 16, pp. 065017, 2016.

International Conferences

1. K. Nirala, M. Gupta and A. Kranti, “Disturbance Induced Refresh Time Lowering in Nanowire RFET 1T-DRAM Array,” 2024 Solid State Devices and Materials (SSDM 2024). (Accepted).
2. S. Semwal, M. Gupta and A. Kranti, “Extremely High Noise Margin and Low Leakage in ULP Circuits with NCFETs,” 2024 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA 2024), pp. 1-2, Hsinchu, Taiwan, 2024.
3. Ruma S R, V. P. H. Hu and M. Gupta, “Improved Process Induced Threshold Voltage Variability in Negative Capacitance Junctionless Transistors,” 8^th IEEE Electron Devices Technology and Manufacturing (EDTM) Conference, pp. 1-3, Bengaluru, India, 2024. 
4. Semwal, N. Rai, R. K. Nirala, M. Gupta and A. Kranti, “Quantum Confinement Imposed Constraints in ULP Circuits with Junctionless FET,” 8^th IEEE Electron Devices Technology and Manufacturing (EDTM) Conference, pp. 1-3, Bengaluru, India, 2024. 
5. Ruma S R and Manish Gupta, Intrinsic Gate Delay in Negative Capacitance Junctionless and Inversion Mode Transistors, “In Abstracts of 22^nd International Workshop on the Physics of Semiconductor Devices (IWPSD 2023), IIT Madras, India, 2023. 
6. M. Gupta and V. P. H. Hu, “Sensitivity Analysis of Ferroelectric Junctionless Transistors for Non-Volatile Memory Applications,” International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), pp. 1-2, Hsinchu, Taiwan, 2023.
7. M. Gupta and V. P. H. Hu, “Optimization of Junctionelss Ferroelectric Field-Effect Transistors for Non-Volatile Memory Applications,” 2021 Solid State Devices and Materials (SSDM), pp. 139-140, Japan, 2021.
8. M. Gupta and V. P. H. Hu, “Improved Switching Time in Negative Capacitance Junctionless Transistor,” 2021 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), Hsinchu, Taiwan, pp. 1-2, 2021.
9. M. Gupta and V. P. H. Hu, “Influence of Channel Doping on Junctionless and Negative Capacitance Junctionless Transistors,” International Electron Devices and Material Symposium (IEDMS), Taiwan, 2020. 
10. M. Gupta and V. P. H. Hu, “Subthreshold Behaviour of Ferroelectric Junctionless Transistor,” 2020 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA 2020), Hsinchu, Taiwan, pp. 1-2, 2020. (Poster presentation)
11. M. Gupta and V. P. H. Hu, “Comparative Analysis of Negative Capacitance Inversion Mode and Junctionless Transistor for Low Power Applications” IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, San Jose, USA, pp. 1-2, 2019.
12. A. Kranti and M. Gupta, “Junctionless Device Cross-section: A key Aspect for Overcoming Boltzmann Tyranny” (Invited talk at 237^th ECS meeting), Montreal, Canada, 2020.
13. M. Gupta, and A. Kranti, “Optimization of Multiple Physical Phenomena through a Universal Metric in Junctionless Transistors,” 32^nd International Conference on VLSI Design and 18^th International Conference on Embedded System, New Delhi, India, 2019. 
14. M. Gupta, and A. Kranti, “Hysteresis Free sub-60 mV/dec Subthreshold Swing in Junctionless MOSFETs,” 31^st International Conference on VLSI Design and 17^th International Conference on Embedded System, Pune, India, pp. 133-38, 2018. 
15. M. Gupta, and A. Kranti, “Device and Material Considerations for Steep Switching MOSFETs,” In Abstracts of 6^th International Symposium on Integrated Functionalities (ISIF 2017), New Delhi, India. 
16. M. Gupta, and A. Kranti, “Steep Current Transition in Germanium Junctionless Transistor,” Electron Devices and Solid-State Circuits (EDSSC), Hsinchu, Taiwan, pp. 1-2, 2017.
17. M. Gupta, and A. Kranti, “Suppressing Single Transistor Latch Effect in Energy Efficient Steep Switching Junctionless MOSFETs,” 30^th International Conference on VLSI Design and 16^th International Conference on Embedded System, Hyderabad, India, pp. 441-46, 2017. 
18. M. Gupta, and A. Kranti, “Influence of Sidewall Spacer Thickness on Steep Switching in Ge Junctionless MOSFETs,” International Conference on Emerging Electronics (ICEE), Mumbai, India, pp. 1-4, 2016. 
19. M. Gupta, and A. Kranti, “Impact of Sidewall Spacer on Steep Subthreshold Swing in Junctionless MOSFETs,” In Abstracts of 18^th International Workshop on the Physics of Semiconductor Devices (IWPSD), Bengaluru, India, pp. 401, 2015.