13.     Sahith, U. Anil Kumar, Vignesh and Syed Ershad Ahmed. “Design Methodology for Highly Accurate Approximate Multiplier for Error Resilient Applications,” Computers and Electrical Engineering (2023). [Accepted] 

 12.     U. Anil Kumar, Vignesh and Syed Ershad Ahmed. “Compressor based Hybrid Approximate Multiplier Architectures with Efficient Error Correction Logic,” Computers and Electrical Engineering (2022). [Accepted] 

 11.     U. Anil Kumar, Sahith and Syed Ershad Ahmed. “Design and Exploration of Low Power SAD Architectures using Approximate Compressors for Integer Motion Estimation,” Microprocessor and Microsystem (2022). [Accepted] 

10.     U. Anil Kumar, Avinash, Vignesh, Suresh and Syed Ershad Ahmed. “CAAM: Compressor-based Adaptive Approximate Multipliers for Neural Network Applications ,” IEEE Embedded Systems Letters (2022). [Accepted] 

 9.  Aroondhati, Smriti, U. Anil Kumar,  and Syed Ershad Ahmed, “A General Methodology to Optimize Flagged Constant Addition ,”Journal of Circuits, Systems and Computers (2022) [Accepted]  

8.     U. Anil Kumar, Sumit Kumar and Syed Ershad Ahmed. “Low-Power Compressor-based Approximate Multipliers with Error-Correcting Module ,” IEEE Embedded Systems Letters (2021).   

 7.   Syed Ershad Ahmed and Mohan, “An Efficient Hardware Approach for Approximate Logical Computation ,”Journal of Circuits, Systems and Computers (2021) 

6.   U. Anil Kumar, Sahith, Sumit Chatterjee, and Syed Ershad Ahmed, “A High-Speed and Power-Efficient Approximate Adder for Image Processing  Applications ,”Journal of Circuits, Systems and Computers (2021). 

5.    Nambi, Suresh, U. Anil Kumar, Kavya Radhakrishnan, Mythreye Venkatesan, and Syed Ershad Ahmed. “DeBAM: Decoder Based Approximate Multiplier for Low Power Applications,” IEEE Embedded Systems Letters (2020).  

4.  U. Anil Kumar and Syed Ershad Ahmed, ” Hardware Efficient Approximate Multiplier Architectures for Media Processing Applications,” Circuit World.  (2021)    

3.    U. Anil Kumar and Syed Ershad Ahmed, “Compressor based Approximate Multiplier Architectures for Media Processing Applications,” International Journal of Electrical & Computer Engineering,  Vol 11, No.4, Aug 2021 

2.  Syed Ershad Ahmed and M. B. Srinivas, “An improved logarithmic multiplier for media processing.” Journal of Signal Processing Systems  (2019): 561-574 

1.Syed Ershad Ahmed, Santosh Varma, and M. B. Srinivas, “Improved designs of digit-by-digit decimal multiplier.” Integration 61 (2018): 150-159.