Start-up Research Grant (SRG) Sponsored by DST-SERB
Role: Principal Investigator
Cost: Rs. 9 Lakhs
Title: A Novel 2:1 Multiplexer based Approach to Implement Ternary Logic Circuits
Duration: 2 Years, Jan 2021 - Jan 2023
Outcomes: (Novel Designs of 2:1 Multiplexer based Combinational and Sequential Circuits)
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"Novel Design Methodologies for CNFET-Based Ternary Sequential Logic Circuits", published in IEEE Transactions on Nanotechnology, vol. 21, pp. 289-298, 2022.
- "Design of CNTFET-based Ternary Logic circuits using Low power Encoder," published in IEEE International Symposium on Smart Electronic Systems (iSES), Warangal, India, 2022, pp. 142-147.
Additional Competitive Research Grant Sponsored by BITS-Pilani
Role: Principal Investigator
Cost: Rs. 4.7 Lakhs
Title: RISC-V-based Approximate Processor and its FPGA Prototype for Image Processing Applications
Duration: 2 Years 9 months, Sept 2019 - June 2022
Outcomes: (RISC V-based Approximate Co-processor, ASIC/FPGA Based Designs for Arithmetic Circuits)
- "Accuracy Reconfigurable Carry Bypass Approximate Adder Integrated as a Co-processor for RISC-V", (VDAT 2023)
- "An Approximate Full-Adder to Eliminate Carry Propagation in Lower Significant Stage of a Multi-Digit Adder," published in International Conference on Computer, Electronics & Electrical Engineering & their Applications (IC2E3), Srinagar Garhwal, India, 2023, pp. 1-6.
- “Design of Resource Efficient Binary and Floating Point Comparator Using FPGA Primitive Instantiation," published in Journal of Circuits, Systems and Computers (World Scientific), Volume 33, No. 2 2450024, 2024.
Research Initiation Grant (RIG) Sponsored by BITS-Pilani
Role: Principal Investigator
Cost: Rs. 2 Lakhs
Title: Design and Synthesis Methodologies for CNFET-based Multi-Valued Logic Circuits
Duration: 2 Years, Jan 2019 - Jan 2021
Outcomes: (New CNFET-based ternary Logic circuits)
- "A Novel Low Power Ternary Multiplier Design using CNFETs," published in 33rd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2020.
- "Design of CNTFET-Based Ternary ALU Using 2:1 Multiplexer Based Approach," published in IEEE Transactions on Nanotechnology, vol. 19, pp. 661-671, 2020.
- "Design of CNFET-based Low-Power Ternary Sequential Logic circuits," published in 21st International Conference on Nanotechnology (NANO), 2021
An Institute of Eminence
