Email: ssdan@hyderabad.bits-pilani.ac.in                Official designation: Associate Professor

 

Office: H233               Residence: H2-402               Phone: +91 40 6630 3692               Fax: +91 40 6630 3998

After graduating from Jadavpur University (J.U.), India, in 2006, Surya Shankar Dan joined the Indian Institute of Science (I.I.Sc.) Bangalore, India, where he earned his doctoral degree in 2009. During his Ph.D., he developed a quantum physics-based compact analytical model for sub-5 nm single electron transistor (SET) devices. The SET model successfully describes the quantum effects influencing the behavior of SET devices and their circuits at the nanoscale regime with mathematical precision. For the first time, he introduced the term "Quantization Threshold," which estimated the maximum cumulative influence of all the quantum effects a sub-10 nm device can withstand before its circuit performance deteriorates. After his Ph.D., he worked as a Scientist at the prestigious Swiss Federal Institute of Technology Lausanne (E.P.F.L.), Switzerland, successfully developing a methodology to accurately determine the lateral junction steepness of a tunnel field effect transistor (TFET). Currently, this technique provides the most precise and accurate estimation of the TFET lateral junction steepness (within the maximum error limits of ±2 Å/decade change in the doping levels across the junction) using simple I-V characterization data. In 2012, he joined as an Assistant Professor in the Dept. of Electrical Engineering (EE), Indian Institute of Technology Hyderabad (I.I.T.H.). After that, he joined as an Assistant Professor in the Dept. of Electronics & Electrical Communication Engineering (E & ETCE), Indian Institute of Technology Kharagpur (I.I.T.KGP) in 2013. Since 2016, he has been with the Dept. of Electronics and Electrical Engineering (EEE), Birla Institute of Technology & Science (B.I.T.S.) Pilani, Hyderabad Campus. Since 2012, he has designed an advanced Gate-Overlap Tunnel FET (GOTFET) device and developed its comprehensive physics-based compact analytical model for the novel Complementary GOTFET (CGOT) technology and used it to design ultra-low-power VLSI circuits for digital, analog, and ternary applications, which outperform its equivalent CMOS designs at the 45 nm technology node. He has recently started exploring memristor devices with novel 2D materials and applying machine learning (ML) approaches, developing their data-driven models for designing efficient VLSI circuits. His current research aspirations also involve the application of data-driven approaches on the physics-based models of state-of-the-art 3D sub-28 nm FinFET devices for the optimal performance of their analog, digital, and ternary VLSI circuits. His research on SET devices (during his Ph.D.) was awarded the "Gold Medal for Best Ph.D. Thesis" in I.I.Sc. His innovative work on GOTFET has been awarded the "Best Research Award" on International Research Awards on New Science Inventions 2021.