Associate Professor, Department of Mechanical Engineering,
BITS Pilani, Pilani Campus
Title: A PROCESS FOR PRODUCING FALSE CEILING TILES AND THE COMPOSITION THEREOF (IN Application: 202411053938),
Inventors: Srikanta Routroy, Khalid Ansari, Anupam Singhal, Rahul Samyal and Arun Kumar Jalan Filed on dated 15 July 2024.
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