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Dr. Abhijit Rameshwar Asati

Professor, Department of Electrical and Electronics Engineering, BITS Pilani, Pilani Campus

High Performance VLSI Data Path Design, Microprocessor Design, Micro-coded Controller Design, NBTI Degradation Issues
Department of Electrical and Electronics Engineering, Birla Institute of Technology & Science, Pilani- 333031, Rajasthan. India.
Abhijit Asati

Research Areas 

 (a)VLSI design, Micro/ Nano electronics, VLSI test, CAD for VLSI

 (b) Embedded system design, high level synthesis

 (c) Hardware development for image processing applications

 (d) Artificial intelligence and machine learning applications

 (e) Artificial intelligence and machine learning hardware design etc.

 

  


Research Interest; Ph.D. Guided and Current Research Students

(A) Research Interest

  • Low power /High speed VLSI Design 
  • Micro/ Nano Electronics (Digital/Analog)
  • NBTI Degradation Issues
  • Embedded System Design
  • Image Processing Hardware
  • High Level Synthesis
  • Artificial Intelligence/ Machine Learning Application
  • Artificial Intelligence/ Machine Learning  Hardware
  • Post quantum cryptography 
  • Hardware security 
  • VLSI CAD
  • VLST Test and Testability
 
(B) Research Students (Ph. D. Completed)
 
(1) Vineet Kumar (2008PHXF433P): Full Time (Own funding)

Topic: Iris Localization in Iris Recognition System: Algorithms and Hardware Implementation  

(Role: Supervisor, Status:  Awarded, Viva-voce examination on 10 March 2017)
 

(2) Ashish Mishra (2009PHXF0038P): Full Time (Own funding)

 Topic: Framework for Translation of C/C++ Applications on Reconfigurable Computing Systems 

(Role: Co-supervisor, Status: Awarded , viva-voce examination on 16 November 2017)

 (3) Priya Gupta (2011PHXF0416P): Full Time (Institute funding)

Topic: Design Exploration of Low Power Arithmetic and SRAM Circuits using Subthreshold Design Technique 

(Role: Co-supervisor, Status: Awarded,  viva-voce examination on 20 February 2018 )
 
(4)   Prateek Sikka (2017PHXP0501P): Part Time
NXP Semiconductor Noida, Topic: "Methodologies for Area, Speed, and Power Optimizations in High-Level Synthesis for Diverse Applications"  
 (Role: Supervisor, Status: Awarded,  viva-voce examination on 2 December 2021)
 
 
(C) Current Research Students:
 
(1) Ms. Jyoti Pandey, (2018PHXP0412P): Full Time 
Exploration of Convolutional Neural Networks and Hardware Implementation of Optimized Network with Improved characteristics
(2) Ms. Divya Vyas (2021PHXP0431P): Full Time 
 Optimization and Implementation of Lattice-Based Post Quantum Cryptographic Algorithms
 
 
(D) DAC member for the following Research Students:
 
(1)  Jai Gopal Pandey (2008PHXF018P), Topic: "Architectures and Algorithms for Image and Video Processing Using FPGA based Platforms" ( Status: Awarded)
 
(2) Nitin Chaturvedi (2007PHXF401P), Topic: "Techniques to improve the performance of cache memory for multi-core processors" ( Status: Awarded)
 
(3) Sneh Lata Murotiya (2010PHXF026P), Topic: "Low-Power High-Speed and Compact Ternary VLSI Circuit Designs using Carbon Nanotube Field Effect Transistors" ( Status: Awarded)
 
(4) Kavindra Kandpal (2014PHXF0601P), Topic: "Investigations on Electronic Behavior and Stability Issues of Zinc Oxide (ZnO) based Thin-Film Transistors (TFTs)" ( Status: Awarded)
 
(5) Tejasvi Alladi (2017PHXF0433P), "Security Provisioning for Emerging Applications in Smart Cities" (Status: Awarded) 
(6)  Gorla Praveen (2019PHXF0028P) "Resource Provisioning and Management of Smart and Sustainable 5G Small Cells Base Stations," (Status: Submitted)